D1の竹中がIEEE Symposium on VLSI Technology and Circuits 2025で2件の発表を行いました（2025/6/13）

発表タイトル：
An 11.9-ENOB 560-MS/s Subranging ADC Employing Amplifier-Switching Architecture with Multi-Threshold Comparators (Best Student Paper Award Finalist)
A 76.5-dB Dynamic-Range 8-bit 100-MS/s Variable-Range SAR ADC