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楊研究員がSymposium on VLSI Circuits 2022で発表しました(2022/06/14)
発表タイトル:
A 10-GHz Inductorless Cascaded PLL with Zero-ISF Subsampling Phase Detector Achieving -63-dBc Reference Spur, 175-fs RMS Jitter and -240-dB FOM
jitter