Integrated Circuits Iizuka Laboratory, Department of Electrical Engineering and Information Systems, The University of Tokyo


D2 Zhang presented his research at International Solid-State Circuits Conference (ISSCC) 2025 (2025/2/19)

Presentation Title:
A 96fsrms-Jitter, −70.6dBc-Fractional-Spur Cascaded PLL Employing Two MMDs with Shared-DSM for Quantization Noise Cancellation