- M. Ikeda, J. H. Lee, T. Zhang, and K.Asada,
"Power Reduction and Performance Improvement in VLSIs,"
1996 IEICE Biwako Workshop, pp.41-45, Sep. 1996,
- 渡部 亮太, 秋田 純一, and 浅田 邦博,
"An Implementation on CMOS Circuit of Tree Structure of Automata for Image Scanning,"
1996年テレビジョン学会年次大会, 3ー6, Jul. 1996,
- 秋田 純一, 渡部 亮太, and 浅田 邦博,
"A Novel Tree Structure of Automata for Selective Scanning of Image Signals,"
1996年テレビジョン学会年次大会, 1996/03/07, Jul. 1996,
- 池野 理門, 伊藤 浩, 名倉 徹, and 浅田 邦博,
"Evaluation of SOI MOSFET Threshold Voltage using 1-D Device Simulation,"
電子情報通信学会 シリコン材料・デバイス研究会、SDM94-208、, Mar. 1996,
- 浅田 邦博 and 秋田 純一,
"Intelligent Low Power Device and Circuit,"
重点領域研究「知能の極限集積化」特別公開シンポジウム, Mar. 1996,
- 池田 誠 and 浅田 邦博,
"Power Reduction using Variable-Width Scheme in Adder,"
96 電子情報通信学会総合大会, pp.C-555, Mar. 1996,
- 秋田 純一 and 浅田 邦博,
"Image Scanning Method with Data Compression Using Tree Structure of Automata,"
電子情報通信学会春季全国大会, Mar. 1996,
- 三堂 哲寿 and 浅田 邦博,
"Simulation of VLSI Interconnections Considering Inductive Coupling Crosstalk Noise,"
第43回応用物理学会関係連合講演会シンポジウム講演, Mar. 1996,
- 張 子誠 and 浅田 邦博,
"A 3.3ns 8x8 bit Parallel Multiplier Using Regenerative Pass-transistor Logic,"
電子情報通信学会 1996年全国春季大会, Mar. 1996,
- 池野 理門 and 浅田 邦博,
"Stable Solution for SOI MOSFET Simulation by Quasi-Transient Method,"
第43回応用物理学会関係連合講演会, Mar. 1996,
- 池田 誠 and 浅田 邦博,
(in Japanese) "ビット幅可変方式を用いた加算機による消費電力削減,"
電子情報通信学会総合大会, C-555, Mar. 1996,
- 池野 理門 and 浅田 邦博,
(in Japanese) "準過渡解析手法によるSOI MOSFETシミュレーションの安定解法,"
第43回応用物理学会関係連合講演会, 26p-H-3, Mar. 1996,
- 三堂 哲寿 and 浅田 邦博,
(in Japanese) "集積回路内の相互接続配線における誘導性を考慮した伝送線路シミュレーッション,"
第43回応用物理学会関係連合講演会, 26p-H-11, Mar. 1996,
- 小松 聡, 池野 理門, 伊藤 浩, and 浅田 邦博,
(in Japanese) "DTMOSのドレイン電流特性のデザインパラメータ依存性,"
第43回応用物理学会関係連合講演会, 26p-H-4, Mar. 1996,
- 鄭 若丹, 池田 誠, and 浅田 邦博,
"A Synchronous Completion Prediction Adder (SCPA),"
電子情報通信学会総合大会, Cー554, Mar. 1996,
- 三堂 哲寿 and 浅田 邦博,
"Crosstalk Noise Considering Inductive Coupling in Strip Wires in Heterogeneous Insulators,"
回路実装学会 第７回ワークショップ, Jan. 1996,
- 池田 誠, 李 知漢, and 浅田 邦博,
"Power Reduction and Performance Improvement in VLSIs,"
IEICE 琵琶湖ワークショップ, pp.41-45, 1996,
- T. S. Cheung, K.Asada, K.L.Yip, and Y.C.Cheng,
"Low Power CMOS Digital Circuit Design with Reduced Voltage Swing,"
Proc.IEEE TENCON '95, pp.311-314, Nov. 1995,
- T. S. Cheung and K.Asada,
"Clock Separated Logic:A Double-Rail Latch Circuit Technique for High Speed Digital Design,"
Proc.IEEE TENCON '95 IEEE Region 10 Conf.on VLSI, pp.303-306, Nov. 1995,
- R.Ikeno, H.Ito, and K.Asada,
"One-Dimensional Analysis of Subthreshold Characteristics of SOI-MOSFET Considering Quantum Mechanical Effects,"
Special Issue on Computational Electronics,The Fourth International Workshop on Computational Electronics (IWCE-4), Gordon & Breach Science Publishers, pp.65-67, Nov. 1995,