- H. Zhang, K. Asada, and T. S. Cheung,
"A Layout Design Method of High Speed CMOS VLSIs for Minimizing Power Consumption,"
Proc. ASICON 1994, Beijing, China, No.4.38, pp.348-351, Oct. 1994,
- T. S. Cheung, M. K. Song, and K. Asada,
"A Self-Refreshable Analog Memory Using Window Detector,"
Proc. ASICON 1994, Beijing, China, No.3.3, pp.145-148, Oct. 1994,
- 池田 誠 and 浅田 邦博,
"A Power Consumption Reduction Method using Partitioned and Reduced-Swing Bus Lines in High-Level Syntesis ,"
1994年電子情報通信学会 秋季全国大会, A-69, Sep. 1994,
- 張 子誠 and 浅田 邦博,
"High Speed CMOS Logic Circuit Design using Sub-Vdd Interfacing Technique,"
1994年電子情報通信学会 秋季大会, SC-9-5, pp.243-4, Sep. 1994,
- 張 子誠, 李 知漢, and 浅田 邦博,
"A 100MHz Serial Data Synchronizer Using Clock Separated Logic Blocks,"
1994年電子情報通信学会 秋季全国大会 , C-483 pp.161, Sep. 1994,
- 伊藤 浩, 池田 誠, and 浅田 邦博,
"Measurement of Fringing Capacitance with Ring Oscillator in MOS/SOI Device,"
第55回応用物理学会学術講演会, 19p-ZG-5, Sep. 1994,
- H. Hayashi and J. Akita,
"A Method of Optimal State Code Assignment for Reducing Power Consumption in Synchronous Circuits,"
1994年電子情報通信学会 秋季全国大会, A-67, pp.67, Sep. 1994,
- J. Akita, H. Hayashi, and K. Asada,
"An Estimation and Reduction of Power Consumption in Clock Line of Synchronous Flip-Flops,"
1994年電子情報通信学会 秋季全国大会, A-68, pp.68, Sep. 1994,
- M. Lee and K. Asada,
"Ultimate Lower Bound of Power for MOS Integrated Circuits,"
Silicon Materials and Device Research Meeting (SDM), Mar. 1994,
- R. Ikeno and K. Asada,
"High-Speed Method for Device Simulations by Block Division,"
The Japan Society of Applied Physics, Mar. 1994,
- M. Lee and K. Asada,
"Ultimate Lower Bound of power for MOSFET Integrated Circuits,"
Silicon Materials and Device Research Meeting (SDM), Mar. 1994,
- M. Lee and K. Asada,
"A proposal to evaluate switching Energy of Recycled Mechanism of a Device,"
Proceedings of the 1994 IEICE Spring Conference, SC-7, Mar. 1994,
- M. LEE and K. Asada,
"A Proposal to Evaluate Minimum Switching Energy of Recycled Mechanism of MOS Device,"
IEICE Spring Conference, SC-7, Mar. 1994,
- 張 子誠, 宋 敏圭, and 浅田 邦博,
"An Architectural Self-Refreshable Analog Memory System,"
1994年電子情報通信学会 春季大会, Mar. 1994,
- M. Ikeda and K. Asada,
"A Reduced-swing Data Transmission Scheme for Resistive Bus Lines in ULSIs,"
The European Design and Test Conference 1994, Proceedings pp. 546-550, Mar. 1994,
- J. Akita and K. Asada,
"A Method for Reducing Power Consumption of CMOS Logic Based on Signal Transition Probability,"
EDAC-ETC Euro Asic 1994, Feb. 1994,
- 佐藤 純一 and 浅田 邦博,
(in Japanese) "パルテノンによるＲＩＳＣプロセッサの設計ーケーススタディー,"
パルテノン研究会, Oct. 1993,
- R. Ikeno and K. Asada,
"High-Speed Method for Device Simulations by Area Division,"
The Japan Society of Applied Physics, Sep. 1993,
- M. Lee and K. Asada,
"A Newly proposed for Delay Improvement on CMOS/SOI Future Technology,"
SISDEP 93, Vol.5, pp.349-352, Sep. 1993,
- 秋田 純一 and 浅田 邦博,
"A Method of Reducing Power Consumption of CMOS Logic Based on Signal Transition Probability,"
電子情報通信学会 VLSI設計技術研究会, ED-93-83, Sep. 1993,