- M. Ikeda and K. Asada,
"Bus Data Coding with Zero Suppression for Low Power Chip Interface,"
IFIP International Workshop on Logic and Architecture Synthesis, pp.267-274, Dec. 1996,
- T. Mido and K. Asada,
"Delay Model for Microstrip Lines Considering Skin Effect for Over 1GHz Operation,"
回路実装学会 第8回ワークショップ, Nov. 1996,
- M. Ikeda, J. H. Lee, R. Zheng, and K. Asada,
"Power Reduction and Performance Improvement in VLSIs,"
電子情報通信学会 LSI設計技術の未来を考える琵琶湖ワークショップ ポスター発表, pp.41-45, Nov. 1996,
- M. Aoyagi and K. Asada,
"Initial stage of stress-migration phenomenon in aluminum interconnection on semiconductor device,"
Technical Report of IEICE, SDM96-132,, Vol.96, No.360, pp.1-7 , Nov. 1996,
- T. Mido and K. Asada,
"Delay Model for Mictostrip Lines Considering Skin Effect for Over 1GHz Operation,"
JIPC 8th Workshop, Nov. 1996,
- K. Asada and J. Akita,
"A Tree Structure of Automata for Selective Image Scanning and Its Implementation ,"
4th Int'l Conf.of Soft Computing (IIzuka'96 ) , A-4-1, Oct. 1996,
- T. Mido and K. Asada,
"Accurate Capacitance Formulas for VLSI Interconnections Based on Finite Element Analysis,"
Proceedings of ANSYS'96 Conference in Japan, pp.239-245, Oct. 1996,
- T. Mido and K. Asada,
"New Capacitance Formulation and Delay Optimum Aspect Ratio for VLSI Interconnections,"
電子情報通信学会 VLSI設計研究会、通信学会技術報告, VLD96-49,Vol.96, No.259, pp.55-60, Sep. 1996,
- S. Komatsu, R. Ikeno, H. Ito, and K. Asada,
"Design parameter dependence and optimization of drain characteristics of DTMOS,"
電子情報通信学会 VLSI設計研究会、通信学会技術報告, VLD96ー43,Vol.96,No.259, Sep. 1996,
- M. Ikeda and K. Asada,
"Signal Transition Oriented Placement and Routing for Power Reduction,"
電子情報通信学会ソサイエティ大会, SA-2-4, Sep. 1996,
- J. H. Lee and K. Asada,
(in Japanese) "同期式完了予測型加算機,"
電子情報通信学会ソサイエティ大会, C-504, Sep. 1996,
- R. Ikeno and K. Asada,
"Device Dependent Convergence-ability of Matrix Solution in Device Simulation,"
第57回応用物理学会学術講演会, 7a-V-4, Sep. 1996,
- T. Mido and K. Asada,
"Formulation for Three Dimensional Capacitances of Contiguous Interconnections in VLSI,"
1996年電子情報通信学会秋期大会, C-470、p.131, Sep. 1996,
- K. Asada and T. Mido,
"Optimum Aspect Ratio of Cross Section of VLSI Interconnections Considering RC-Delay,"
1996年電子情報通信学会秋期大会, C-471,p,132, Sep. 1996,
- T. Torii and K. Asada,
"A Study of Input Selected Logic Circuit Design Based on Human Procedure,"
電子情報通信学会ソサイエティ大会, A-53, Sep. 1996,
- T. Yamashita and K. Asada,
"An Application of a Latch Sense Amplifier for CPL,"
電子情報通信学会ソサイエティ大会, C-476, Sep. 1996,
- J. Akita and K. Asada,
"An Implementation of Image Scanning Method with Selective Activation of Tree Structure,"
1996年電子情報通信学会秋期大会, A-54, Sep. 1996,
- K. Asada and J. Akita,
"A Selective Image Scanning Method using Tree Structure of Automata and Its Applications,"
1996年電子情報通信学会秋期大会, ES-3-7, Sep. 1996,
- M. Aoyagi and K. Asada,
"Effect of residual stress on stress-migration lifetime in Aluminum interconnection,"
The 57th Fall Meeting, Japan Society of Applied Physics and Related Societies, 8p-N16, Sep. 1996,
- R. Ikeno and K. Asada,
"Robust simulation for the hysteresis phenomena of SOI MOSFET's by Quasi-Transient Method,"
1996 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD'96), P-13, Sep. 1996,