D3 Wang presented his research at IEEE/JSAP Symposium on VLSI Technology and Circuits 2026 (2026/6/19)

Presentation Title:
A 91.9dB-SNDR 100kHz-BW DT ΔΣ ADC Employing Thermal Noise Suppression Techniques with Gain-Switched Dynamic Self-Quenching FIA (Prof. Iizuka presented as a replacement presenter)