D3 Zhang and M2 Ono presented their researches at International Solid-State Circuits Conference (ISSCC) 2026 (2026/2/21)

Presentation Title:
Zhang: A 157fsrms-Jitter, −73dBc-Fractional-Spur, Calibration-Free Cascaded SPLL Employing Robust Feedforward Noise Cancellation and MMD-Based Quantization-Error Cancellation with a 60MHz Reference (Prof. Iizuka presented as a replacement presenter)

Ono: Student Research Preview Presentation