What's "Tetsuhisa MIDO" ?

Japanese version is here.

Tetsuhisa Mido

Ph.D Candidate. (D3)

ASADA Lab. : Graduate school of Engineering,

University of Tokyo

7-3-1, Hongo, Bunkyo-ku, Tokyo, 113 JAPAN.

Tel:+81-3-3812-2111 (ex. 6771)

Fax:+81-3-5800-5797

e-mail:mido@silicon.u-tokyo.ac.jp

Tetsuhisa Mido was born in Ehime, Japan, in 1970. He received the B.S. degrees in electric engineering from the University of Tokyo, Japan, in 1993, and the M.S. degree in electronic engineering from the University of Tokyo, in 1996. He is currently a doctor course student in electronic engineering, the University of Tokyo. He is interested in design and evaluation of CMOS VLSI system for low-power and high-speed application. He is a member of Institute of Electronics, Information and Communication Engineerings of Japan ( IEICEJ), Japan Society of Applied Physics (JSAP)

Graduate Thesis: An optimization of 2-dimensional transistor layout for VLSI

Master Thesis: Optimum Aspect Ratio of VLSI Interconnections Considering Wiring Delay and Crosstalk Noise

Riding MIDO!

My BIKE:CBR400RR('89)

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ASADA LAB. Home Page / Dept. of Electronics Eng., Fac. of Eng., The Univ. of Tokyo. /