- Fig. 1: Sequential Circuits and Path delay
- Fig. 2: D-FF timings: setup and hold time
- Fig. 3: Sequential Circuits and Path delay including FF timings and clock skew
- Fig. 4: Chattering remover
- Fig. 5: Asynchronous reset and synchronous reset
- Fig. 6: Block diagram of a simple microprocessor
- Fig. 7: Register
- Fig. 8: Register with write enable by selector
- Fig. 9: Register with write enable by clock gating
- Fig. 10:Register File
- Fig. 11: Binary counter using incrementer
- Fig. 12: Binary counter using adder
- Fig. 13: Shift register
- Fig. 14: FIFO using counters
